1. Field of the Invention
This invention relates to a concurrently and globally interconnected superconducting computer processor and sensor array. More specifically, this invention relates to an optical computer utilizing fine-grained superconductive material in a focal plane array configured to form a neural network computer architecture.
2. Description of the Prior Art
Superconductivity has not been successfully implemented in a computer design because of the lack of an operative cryogenic memory. Attempts to implement superconductivity in a computer design creates the problem known as the "Von Neuman Bottleneck". This problem initially occurs when conventional superconducting computers use silicon based memories which can not operate effectively at the cryogenic temperatures required by the superconductor logic gate materials. The logic processes are separated from the memory storage. Switching operations can be performed at high speeds but the input and output from memory is hindered. The input/output problems slows down the speed gained from the logic processes of the conventional superconducting computer.
The later use of "Josephson junctions" as the basis for the superconductor switch, as described in U.S. Pat. Nos. 3,626,391 and 3,916,391, creates another problem in applying superconductors in computers. A Josephson junction is a diode and has no appreciable gain (only about a factor of 3). Consequently, signal-over-noise floor threshold technique cannot be used for cascading in computer operations since the noise masks the signal after a few steps.
These low gain conditions are compounded by the magnetic field crosstalk which limits the density of packaging in superconductor chip designs. Although close packaging is generally sought in electronic design, space limitations take on a significant importance for superconductors because the environs must be maintained at cryogenic temperatures.
An additional problem of superconductive systems is that there is no RC time content. Therefore, classical methods of manipulating data with clock cycles and in lock-steps requires tremendous precision in timing.
Very large scale integration (VLSI) can achieve 20,000 gates or more within a chip of about 1.5 square centimeters. However, only a few hundred connections can be made to a VLSI chip because of the two dimensional planar technology and the interference between electric signals cuased by the packing ratio or component density within a chip.
Creating a global wire interconnect communication network with conventional means would require that each input/output be connected to every other input/output. Assuming N number of inputs/outputs, where N is an integer, N.sup.2 interconnects would be required to couple each input/output with every other input/output. As the number of the computer processor elements increases to as many as ten thousand, N.sup.2 becomes an unmanageable number of interconnects to effect by conventional means. An "N.sup.2 bottleneck" exists for a global wire interconnect communications network.
One approach to solve the "N.sup.2 bottleneck" is an optical processor which uses radiation as a communication medium instead of wires. A real-time transparency device is used in optical processors for high-speed parallel data throughput. A transmissive or reflective spatial light modulator (SLM) is an example of such a device. An SLM can be made from liquid crystal, a Titus tube, an electro-optical Pockels's device, optically-addressed light valves, ceramic ferroelectric devices, surface deformation light valves or any other device acting as a two-dimensional optical filter.
Optical processing has not been used with superconducting material because there is a response time scale difference between the SLM and a superconductor. The SLM has a milli- to micro-second response time while a superconductor has a considerably shorter nano- to pico-second response time. If conventional clock cycles were used, the timing difference would make manipulation of data in an optical computer utilizing superconductive material impossible because of the lack of precision in timing.
The sizes of an SLM and a neural network are also incompatible. The Defense Advanced Research Projects Agency (DARPA) has developed an experimental SLM that controls up to 1000.times.1000 points of light or pixels. The only commercially available SLM controls just 100.times.100 pixels. To date, there has been a one-to-one correspondence within the SLM and between the SLM and the data input plane of an optical computer. This correspondence limits an SLM to the same number of light valves as pixels to be controlled. A neural network which is attempting to imitate the human brain would have millions of interconnects. No commercially available or experimental SLM would have the capacity to control such a network under present process control conditions.